module IF_ID(
    input wire clk,
    input wire we,
    input wire reset,
    input wire[31:0] inst,
    input wire[31:0] cur_pc,
    input wire IF_ready,
    input wire exc,
    input wire[5:0] ecode,
    input wire esubcode,
    input wire[31:0]badv,


    output reg[31:0] inst_o,
    output reg[31:0] cur_pc_o,
    output reg IF_ready_o,
    output reg exc_o,
    output reg[5:0] ecode_o,
    output reg esubcode_o,
    output reg[31:0]badv_o
);
    always @(posedge clk) begin
        if(reset)begin
            inst_o <= 32'h02800000;
            IF_ready_o <= 0;
            exc_o <= exc;
            ecode_o <= ecode;
            esubcode_o <= esubcode;
            badv_o <= badv;
        end 
        else if(we)begin
            inst_o <= inst;
            cur_pc_o <= cur_pc;
            IF_ready_o <= IF_ready;
            exc_o <= exc;
            ecode_o <= ecode;
            esubcode_o <= esubcode;
            badv_o <= badv;
        end
    end


endmodule